1. Field of the Invention
The present invention relates to an electrically writable/erasable non-volatile semiconductor memory device. In particular, the present invention relates to a non-volatile semiconductor memory device having a structure in which a read operation and a write/erase operation in connection with a particular memory cell can be simultaneously performed on one chip.
2. Description of the Related Art
FIG. 4 is a circuit configuration diagram of a conventional non-volatile semiconductor memory device (one chip flash memory in which data is erasable on a block basis). According to this conventional example, a floating gate type MOS transistor is used as a non-volatile memory transistor, which has a floating gate and allows data to be written by injection of channel hot electrons and to be erased by tunnel erasing by a Fowler-Nordheim current.
As shown in FIG. 4, in each of memory cell array blocks BL.sub.1, BL.sub.2, . . . , BL.sub.k, the above-mentioned floating gate type MOS transistors are arranged in a matrix. Control gates of the transistors in each identical row are commonly connected to form word lines W.sub.1, W.sub.2, . . . , W.sub.M. Drains of the transistors in each identical column are commonly connected to form bit lines B.sub.1-1, . . . , B.sub.1-N, B.sub.2-1, . . . , B.sub.2-N, . . . , B.sub.K-1, . . . , B.sub.K-N. Furthermore, sources of all the transistors arranged in the matrix are commonly connected so as to form common sources S.sub.1, . . . , S.sub.K. The word lines in each block are commonly connected to the corresponding ones. The memory cell array blocks BL.sub.1, . . . , BL.sub.K respectively have column decoders YD.sub.1, . . . , YD.sub.K which selectively connect the plurality of bit lines to a data bus D-BUS in accordance with a signal value of a column selection signal portion of an input address signal at the time of writing and reading data. The memory cell array blocks BL.sub.1, . . . , BL.sub.K respectively have output circuits SV.sub.1, . . . , SV.sub.K for selectively outputting a predetermined voltage to the common sources S.sub.1, . . . , S.sub.K at the time of writing, erasing, and reading data (i.e., GND (ground voltage) at the time of writing and reading data; V.sub.HH (high voltage) at the time of erasing data). The output circuits SV.sub.1, . . . , SV.sub.K respectively have P-channel MOS transistors P.sub.11, . . . , P.sub.K1 for applying a high voltage V.sub.HH and N-channel MOS transistors N.sub.11, . . . , N.sub.K1 for applying a ground voltage GND. Furthermore, a row decoder XD outputs a predetermined word line selection signal commonly to the word lines of each of the memory cell array blocks BL.sub.1, ..., BL.sub.K in accordance with a signal value of a row selection signal portion of an input address signal. An N-channel MOS transistor N.sub.1 applies a predetermined high voltage V.sub.PP for writing to the data bus D-BUS, and a sense amplifier SA senses, amplifies, and outputs a current of the data bus D-BUS at the time of reading data.
Hereinafter, the operations of the above-mentioned conventional semiconductor memory device will be described.
First, a data write operation will be described. For description, the case where data is written in a memory cell M.sub.2-22 at a crossed point of the word line W.sub.2 and the bit line B.sub.2-2 provided in the memory cell array block BL.sub.2 will be described.
In order to fix the common source S.sub.2 of the memory cell array block BL.sub.2 at a GND level, a control signal P/R.sub.2 is set at "H" to turn on a transistor N.sub.21, whereby the common source S.sub.2 is set at the GND level. Simultaneously, the row decoder XD applies a high voltage of around 10 volts for writing to the word line W.sub.2 based on an input address signal. Then, the column decoder YD.sub.2 connects the data bus D-BUS to the bit line B.sub.2-2. A high voltage is applied to the data bus D-BUS by setting a control signal PGEN at "H", and a voltage of around 6 volts is applied to the bit line B.sub.2-2. This allows a current to flow from the bit line B.sub.2-2 to the source S.sub.2 in the memory cell M.sub.2-22. Hot electrons generated at this time are injected into a floating gate of the memory cell M.sub.2-22. Thus, writing of data is completed.
Secondly, a data erase operation will be described. For description, the case where data is erased from all the memory cells in the memory cell array block BL.sub.2 will be described.
All the word lines W.sub.1, . . . , W.sub.M are set at the GND level by the row decoder XD. Thereafter, control signals ER.sub.2# and P/R.sub.2 are set at "L" so as to set the common source S.sub.2 at a high voltage of around 10 volts during a predetermined period, whereby a high voltage of around 10 volts is applied between sources and control gates of all the memory cells in the memory cell array block BL.sub.2. Electrons are ejected from the floating gates of all the memory cells. Thus, erasing of data is completed.
Finally, a data read operation will be described. For description, the case where data is read from the memory cell M.sub.2-22 at a crossed point of the word line W.sub.2 and the bit line B.sub.2-2 provided in the memory cell array block BL.sub.2 will be described.
The transistor N.sub.21 is turned on by setting the control signal P/R.sub.2 at "H", and the common source S.sub.2 is set at the GND level. A voltage of around 5 volts for reading is applied to the word line W.sub.2 by the row decoder XD, and a voltage of around 1 volt is applied to the bit line B.sub.2-2 via the column decoder YD.sub.2. A current flowing through the memory cells at this time is amplified by the sense amplifier SA. Thus, reading of data is performed.
The time required for the above-mentioned respective operations is as follows: the read operation is performed at a relatively high speed, i.e., about tens of nanoseconds, the write operation usually requires several microseconds to about ten microseconds, and the erase operation requires a relatively long period of time, i.e., about hundreds of milliseconds to about 1 second. The write operation includes a write verifying operation for checking whether or not the threshold value of the memory cell has reached a predetermined value after writing, and further requires a re-write operation if the threshold value has not reached the predetermined value. Therefore, the write operation requires a relatively long period of time.
The erase operation includes a write operation before erasing for the purpose of equalizing the threshold values of all the memory cells at the time of starting erasing, in addition to the erase verifying and re-erase operations similar to the write verifying and re-write operations. Therefore, the erase operation requires the longest period of time.
As described above, the write and erase operations require longer periods of time. Therefore, in the case where it is required to read data from a block while data is being erased or written in another block, a read operation is required to be performed with the erase or write operation being suspended. This is generally called "suspend".
However, the erase or write operation is completely suspended during the read operation. Therefore, in the case of a system in which the read operation is often performed, e.g., a system in which program for controlling a system is stored in a flash memory, it is practically impossible to write data in or erase it from the identical flash memory while reading the system control program (instruction code) stored in the flash memory.
One strategy to overcome the above-mentioned problem is to provide two flash memory devices in a system. In this case, the following problem will remain unsolved.
More specifically, in a mobile phone which is required to be light-weight and miniaturized, it is necessary to minimize the number of devices mounted on a system. Thus, providing two separate devices is disadvantageous. Even when two flash memory devices are used, while data is being read from one flash memory device, data can be written in or erased from only the other device. In other words, once a system is constructed, a region where data is simultaneously read and written or erased cannot be varied. In general, the size of a region where program (instruction code) for controlling a system is stored is different from that of a data region where data is written or erased. The ratio therebetween may be altered even in the identical system in the case where the system is upgraded.
In order to solve the problem related to light-weight and miniaturization, two memory regions in which completely independent operations can be performed may be formed in one flash memory device. FIG. 5 shows one such example. In this example, the word lines are completely isolated from each other at the center thereof to form two word line blocks (W.sub.1-1, W.sub.1-2, . . . , W.sub.1-M) and (W.sub.2-1, W.sub.2-2,. . . , W.sub.2-M), and row decoders XD.sub.1 and XD.sub.2 are provided for the respective blocks. More specifically, memory cell array blocks BL.sub.1 through BL.sub.K/2 are driven by the row decoder XD.sub.1, and the memory cell array blocks BL.sub.K/2+1 to BL.sub.K are driven by the row decoder XD.sub.2.
However, even in this example shown in FIG. 5, data cannot be simultaneously read and written or erased, for example, with respect to the memory cell array blocks BL.sub.1 and BL.sub.2. This is because the memory cell array blocks BL.sub.1 and BL.sub.2 have the word lines in common.
In order to allow the operations of each memory cell array block to be completely independently performed, the memory cell array blocks BL.sub.1, BL.sub.2, . . . , BL.sub.K may be respectively provided with independent word lines (W.sub.1-1, W.sub.1-2,. . . , W.sub.1-M), (W.sub.2-1, W.sub.2-2, . . . , W.sub.2-M), . . . , and (W.sub.K-1, W.sub.K-2, . . . , W.sub.K-M), so that the memory cell array blocks BL.sub.1, BL.sub.2, . . . , BL.sub.K can be respectively driven by completely independent row decoders XD.sub.1, XD.sub.2, . . . , XD.sub.K, as shown in FIG. 6. In this case, a layout area remarkably increases. This is also disadvantageous.